The present invention relates to a communication control device for use in data communication applications, and a communication system using the same.
For a high speed communication control device of a class capable of processing several tens of Mbps to 500 Mbps, it is required to substantially improve the throughput of data transmission and reception, thereby a method of expanding the data bus width for a microprocessor (hereinafter referred to as a CPU) has been used. Conventionally, the bus width for a communication control device has been expanded to accommodate a required large bus width by the following method. Such a conventional method will be described by way of example with respect to a communication control unit which has a data bus width of 16 bits and capable of performing a direct memory access (DMA) data transfer to and which is from a 32 bit CPU, with reference to FIG. 5, which is a schematic diagram of such a conventional communication system.
In FIG. 5, numeral 55 denotes a communication control unit which includes a transmitter, a receiver, a transmission FIFO memory unit, a reception FIFO memory unit and a DMA unit. Normally, the communication control unit is a semiconductor integrated circuit (LSI) device which is provided within a data processing unit for performing data communication between a plurality of data processing units. Numerals 58, 62 denote latch registers which register addresses of data to be transferred. Numeral 60 denotes a comparator which compares addresses registered in the latch registers 58, 62. Further, numeral 63 identifies a buffer memory which temporarily stores transfer data. Numeral 70 denotes a 32 bit CPU, 71 denotes an external memory, and 56 and 57 denote an address bus and a data bus, respectively, of the communication control unit 55. Numerals 65, 66, 67, 68 and 69 denote external buses.
Now, with reference to FIG. 6 the, operation of the above-mentioned communication system will be described. FIG. 6 shows a time chart of an address signal and a data bus signal, wherein, for convenience of explanation, data bus 57 is assumed to have a width of 16 bits and external buses 65-69 are assumed to have a width of 32 bits.
In the case of a DMA transfer of data, having a data bus width of 16 bits, between external memory 71, via external bus 67, having a data bus width of 32 bits, and the communication control unit 55, at one cycle of its DMA transfer, an address ADR1 of data which is an object of a current data transfer is transferred via address bus 56 of the communication control unit 55 so as to be registered in latch register 58. Then, lower data DAT1 is transferred via data bus 57 of the communication control unit 55 so as to be stored in buffer 63.
Then, at a second cycle of its DMA transfer, a next address ADR2 is transferred via address bus 56 so as to be registered in latch register 62, and higher data DAT2 is then transferred via data bus 57 of the communication control unit 55 so as to be stored in buffer 63. After confirmation of the values in the latch registers, it is determined in comparator 60 whether these addresses ADR1 and ADR2 are continual or not. If they are continual addresses, a coincidence signal is output to buffer 63 via a signal line 64. Responsive to this signal, buffer 63 produces to external bus 66 the 32 bit data DAT3 comprising data DAT1 and DAT2, thereby performing data transfer to the external memory 71.
In the conventional communication system as described above, there is a disadvantage in that, since a discrimination circuit to determine whether addresses of data for transfer are continual or not is required, the size of the communication system becomes large.